UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 332

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0/Kx2-L
7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51
(1) Timer clock selection register 5n (TCL5n)
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
The following five registers are used to control 8-bit timer/event counters 50 and 51.
• Timer clock selection register 5n (TCL5n)
• 8-bit timer mode control register 5n (TMC5n)
• Port alternate switch control register (MUXSEL) (78K0/KA2-L (25-pin products) only)
• Port mode register 0 (PM0), port mode register 1 (PM1), or port mode register 3 (PM3)
• Port register 0 (P0), port register 1 (P1), or port register 3 (P3)
Notes 1.
Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand.
Remark f
This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input.
TCL5n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears TCL5n to 00H.
Remark 78K0/KY2-L, 78K0/KA2-L: n = 1
Address: FF6AH
Symbol
TCL50
Figure 7-7. Format of Timer Clock Selection Register 50 (TCL50) (78K0/KB2-L, 78K0/KC2-L Only)
2.
2. Be sure to clear bits 3 to 7 to “0”.
PRS
78K0/KB2-L, 78K0/KC2-L: n = 0, 1
If the peripheral hardware clock (f
operating frequency varies depending on the supply voltage.
• V
• V
Do not start timer operation with the external clock from the TI50 pin when the internal high-speed
oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.
: Peripheral hardware clock frequency
DD
DD
TCL502
= 2.7 to 5.5 V: f
= 1.8 to 2.7 V: f
7
0
0
0
0
0
1
1
1
1
After reset: 00H
TCL501
6
0
0
0
1
1
0
0
1
1
PRS
PRS
≤ 10 MHz
≤ 5 MHz
R/W
TCL500
5
0
0
1
0
1
0
1
0
1
PRS
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
) operates on the high-speed system clock (f
TI50 pin falling edge
TI50 pin rising edge
f
f
f
f
f
f
PRS
PRS
PRS
PRS
PRS
PRS
/2
/2
/2
/2
/2
4
0
2
6
8
13
2 MHz
1 MHz
500 kHz
31.25 kHz
7.81 kHz
0.24 kHz
f
PRS
3
0
= 2 MHz
Note 2
Count clock selection
Note 2
TCL502
5 MHz
2.5 MHz
1.25 MHz
78.13 kHz
19.53 kHz
0.61 kHz
2
f
PRS
= 5 MHz
Note 1
TCL501
1
10 MHz
5 MHz
2.5 MHz
156.25 kHz
39.06 kHz
1.22 kHz
XH
f
PRS
) (XSEL = 1), the f
= 10 MHz
TCL500
0
318
PRS