UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 662

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UPD78F0552MA-FAA-AX

Manufacturer Part Number
UPD78F0552MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0552MA-FAA-AX

Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
78K0/Kx2-L
Remarks 1.
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Item
System clock
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event counter 00
8-bit timer/event
counter
8-bit timer
Real-time counter (RTC)
Watchdog timer
Clock output
A/D converter
Operational amplifiers 0, 1
Serial interface
Key interrupt
Power-on-clear function
Low-voltage detection function
External interrupt
Main system clock
Subsystem clock
f
IL
2.
STOP Mode Setting
f
f
f
The functions mounted depend on the product.
Functions.
IH
EXCLK
EXCLKS
:
UART6
CSI10
CSI11
IICA
: External main system clock,
: External subsystem clock,
Internal high-speed oscillation clock,
f
f
f
f
f
IH
X
EXCLK
XT
EXCLKS
H0
H1
50
51
Clock supply to the CPU is stopped
Stopped
Input invalid
Status before STOP mode was set is retained
Operates or stops by external clock input
Status before STOP mode was set is retained
Operation stopped
Status before STOP mode was set is retained
Operation stopped
Operable only when TI50 is selected as the count clock
Operable only when TI51 is selected as the count clock
Operable only when TM50 output is selected as the count clock during 8-bit timer/event counter
50 operation
Operable only when f
Operable
Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Operable only when subsystem clock is selected as the count clock
Operation stopped
Operable
Operable only when TM50 output is selected as the serial clock during 8-bit timer/event counter
50 operation
Operable only when external clock is selected as the serial clock
Wakeup by address match operable
Operable
When CPU Is Operating on
Oscillation Clock (f
Internal High-Speed
Table 19-3. Operating Statuses in STOP Mode
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock
IL
, f
IH
IL
)
/2
6
, f
IL
/2
15
When CPU Is Operating on
is selected as the count clock
f
f
f
X
XT
IL
: X1 clock
: Internal low-speed oscillation clock
: XT1 clock
Refer to 1.4
X1 Clock (f
X
CHAPTER 19 STANDBY FUNCTION
)
Block Diagram and 1.5
External Main System Clock
When CPU Is Operating on
(f
EXCLK
)
Outline of
648

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