UPD78F0552MA-FAA-AX Renesas Electronics America, UPD78F0552MA-FAA-AX Datasheet - Page 697

• Manufacturer Part Number: UPD78F0552MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0552MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
22.4.2 When used as interrupt
(1) When detecting level of supply voltage (V
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(a) When LVI default start function stopped is set (LVISTART = 0)
• When starting operation
• When stopping operation
Figure 22-8 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this
timing chart correspond to <1> to <9> above.
•
•
Either of the following procedures must be executed.
Write 00H to LVIM.
Clear LVION to 0.
<1>
<2>
<3>
<4>
<5>
<6>
<7>
<8>
<9>
<10> Execute the EI instruction (when vector interrupts are used).
When using 8-bit memory manipulation instruction:
When using 1-bit memory manipulation instruction:
Mask the LVI interrupt (LVIMK = 1).
Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage
Set the LVI detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level
Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected)
(default value).
Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
Use software to wait for an operation stabilization time (10
Confirm that “supply voltage (V
Clear the interrupt request flag of LVI (LVIIF) to 0.
Release the interrupt mask flag of LVI (LVIMK).
(V
selection register (LVIS).
or “supply voltage (V
(LVIF) of LVIM.
DD
)) (default value).
DD
) < LVI detection voltage (V
DD
DD
) ≥ LVI detection voltage (V
)
LVI
CHAPTER 22 LOW-VOLTAGE DETECTOR
)” when detecting the rising edge of V
μ
s (MAX.)).
LVI
)” when detecting the falling edge of V
DD
, at bit 0
683
DD
,