D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 932
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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22.6.6
This HCAN2 supports clock gating to reduce power consumption. The module standby mode can
be controlled by CLKSTP00 (bit 12 for channel 0 and bit 13 for channel 1) in the Low Power
Consumption Module.
To set one of HCAN2 channels to standby mode, the following procedure is required:
1. Set HCAN2 to Halt Mode (MCR1 = 1).
2. Wait for the Halt Mode Interrupt (IRR0).
3. Clear all pending interrupt requests.
4. Disable the requested channel by setting the corresponding bit to 1 in CLKSTP00 register in
To wake-up from the Standby mode, the following procedure is required:
1. Enable the requested channel by setting the corresponding bit to 1 in CLKSTPCLR00 register
2. Modify HCAN2 configurations, if necessary
3. Release HCAN2 Halt Mode by clearing MCR1.
4. After 11 recessive bits are detected on the CAN bus, the HCAN2 is able to join the
22.7
22.7.1
Although transmission is possible in the Self Tests with the master control register (MCR) TST4
bit set to 1 (auto- acknowledge mode), reception of the transmitted data is not possible.
22.7.2
Do not access mailboxes when the HCAN2 module is in the sleep state. The CPU may stop if a
mailbox is accessed during HCAN2 sleep mode. The CPU will not stop if registers other than the
mailbox registers are accessed during HCAN2 sleep mode. Furthermore, the CPU will not stop if a
mailbox is accessed during any state other than HCAN2 sleep mode.
Rev. 2.00 Feb. 12, 2010 Page 848 of 1330
REJ09B0554-0200
the Power Control (channel 0 for CSTP12, channel 1 for CSTP13).
in the Power Control (channel 0 for bit 12, channel 1 for bit 13).
communication.
Standby Mode
Usage Notes
Auto-Acknowledge Mode Usage Note
Mailbox Access during HCAN2 Sleep Mode
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