D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 685
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Part Number:
D17760BP200AD
Manufacturer:
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Quantity:
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D17760BP200ADV
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17.3.14 Serial Error Register (SCRER)
SCRER is a 16-bit register that indicates the number of receive errors in the data in SCFRDR.
SCRER can always be read from the CPU.
Initial value:
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W:
Bit:
Bit Name
—
PER6
PER5
PER4
PER3
PER2
PER1
PER0
—
FER6
FER5
FER4
FER3
FER2
FER1
FER0
15
R
0
-
PER6 PER5 PER4 PER3 PER2 PER1 PER0
14
R
0
13
R
0
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
12
R
0
11
R
0
10
R
0
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
9
0
Description
Reserved
This bit is always read as 0. The write value
should always be 0.
Number of Parity Errors
These bits indicate the number of data bytes in
which a parity error occurred in the receive data
stored in SCFRDR.
After the ER bit in SCFSR is set, the value
indicated by bits PER6 to PER0 is the number of
data bytes in which a parity error occurred.
If all 128 bytes of receive data in SCFRDR have
parity errors, the value indicated by bits PER6 to
PER0 will be 0.
Reserved
This bit is always read as 0. The write value
should always be 0.
Number of Framing Errors
These bits indicate the number of data bytes in
which a framing error occurred in the receive data
stored in SCFRDR.
After the ER bit in SCFSR is set, the value
indicated by bits FER6 to FER0 is the number of
data bytes in which a framing error occurred.
If all 128 bytes of receive data in SCFRDR have
framing errors, the value indicated by bits FER6 to
FER0 will be 0.
R
8
0
R
7
0
-
Rev. 2.00 Feb. 12, 2010 Page 601 of 1330
FER6 FER5 FER4 FER3 FER2 FER1 FER0
R
6
0
5
0
R
R
4
0
3
0
R
REJ09B0554-0200
R
2
0
1
0
R
R
0
0
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