D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 150
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Manufacturer:
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Example: If the double-precision FSUB instruction (FSUB DR0, DR2) is executed with input
data DR0 = H'C1F00000 80000000, DR2 = H'C4B250D2 0CC1FB74, and FPSCR = H'000C0001,
the correct operation result is DR2 = H'C4B250D2 0CC1F973, and FPSCR.Flag.I and
FPSCR.Cause.I should be set to 1. However, the result actually produced by the FPU is DR2 =
H'C4B250D2 0CC1F974, and FPSCR.Flag.I and FPSCR.Cause.I are not set to 1.
Effects: In addition to the problem described above, the numerical size of the result of the
operation may contain a minute operation error equivalent to 1/256 of the LSB of the mantissa of
the unrounded value. This is can be described as within the scope of the subsequent rounding
mechanism. Strictly speaking, it consists of the following.
a: The infinite-precision operation result
b: The closest expressible value less than a
c: The closest expressible value greater than a
d: The operation result when a is rounded correctly
e: The operation result when a is rounded by the FPU
• The rounding error when rounding is performed correctly in Round to Nearest mode is:
• The rounding error when rounding is performed correctly in Round to Zero mode is:
Rev. 2.00 Feb. 12, 2010 Page 66 of 1330
REJ09B0554-0200
0 ≤ | d − a | ≤ (1/2) × (c − b)
And the rounding error when rounding is performed by the FPU is:
0 ≤ | e − a | < (129/256) × (c − b)
If c – b is considered the LSB of the mantissa, the range of rounding error is equivalent to
1/256 of the LSB of the mantissa of the correctly rounded value.
(−1) × (c − b) < | d |−| a | ≤ 0
And the rounding error when rounding is performed by the FPU is:
(−1) × (c − b) < | e |−| a | < (1/256) × (c − b)
If c – b is considered the LSB of the mantissa, the range of rounding error is equivalent to
1/256 of the LSB of the mantissa of the correctly rounded value.
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