D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 493
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D17760BP200AD
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
D17760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit
4
3
2
1
0
Notes: 1. Internal priority of the DMABRG: LCDC > A−B−C−D*
2. A = HAC(0)/SSI(0) transmission, B = HAC(0)/SSI(0) reception, C = HAC(1)/SSI(1)
3. A−B−C−D is the round-robin method.
4. This bit is not set to 1 when TMU channel 2 (input capture interrupt) or auto-request has
5. This bit is not set to 1 when DREQ1 is accepted in external request 2-channel mode.
6. This bit is not set to 1 when DREQ0 is accepted in external request 2-channel mode.
7. An address error (DMAOR.AE=1) or an NMI interrupt (DMAOR.NMIF=1) may result in
Bit Name
AL1
—
DS0
RL0
AL0
transmission, and D = HAC(1)/SSI(1) reception
been accepted.
REXn=1 although the corresponding channel accepts a DMA transfer request. For
details of an address error or NMI interrupt, refer to (2) Ending Transfer Simultaneously
on All Channels, in section 11.4.6 Ending DMA Transfer.
Initial Value
0
0
0
0
0
R/W
R/W
R
R/W
R/W
R/W
Description
Acknowledge Level 1
0: DACK1 high-active
1: DACK1 low-active
Reserved
This bit is always read as 0. The write value
should always be 0.
DREQ0 Select
0: Low-level detection
1: Falling-edge detection
Request Check Level 0
0: DRAK0 high-active
1: DRAK0 low-active
Acknowledge Level 0
0: DACK0 high-active
1: DACK0 low-active
Rev. 2.00 Feb. 12, 2010 Page 409 of 1330
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REJ09B0554-0200
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