D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 526
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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D17760BP200AD
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• Burst Mode, Single Address Mode, Level Detection
• Burst Mode, Dual Address Mode, Edge Detection
• Burst Mode, Single Address Mode, Edge Detection
(4) Suspension of DMA Transfer with DREQ Level Detection
With DREQ level detection in burst mode or cycle steal mode, and in dual address mode or single
address mode, the external device for which DMA transfer is being executed can determine at the
rising edge of CKIO that DRAK has been asserted, and suspend DMA transfer by negating
DREQ. In this case, the next DRAK signal is not output.
Rev. 2.00 Feb. 12, 2010 Page 442 of 1330
REJ09B0554-0200
DREQ sampling timing in burst mode using single address mode and level detection is shown
in figure 11.20.
In the example shown in figure 11.25, DMAC transfer begins, at the earliest, four CKIO cycles
after the first sampling operation, and the second sampling operation begins one cycle after the
start of the first DMAC transfer bus cycle.
In single address mode, the DACK signal is output every DMAC transfer cycle.
In figure 11.29, with a 32-byte data size, 32-bit bus width, and SDRAM: row hit write, DMAC
transfer begins, at the earliest, six CKIO cycles after the first sampling operation. The second
sampling operation begins one cycle after DACK is asserted for the first DMAC transfer.
In burst mode using dual address mode and edge detection, DREQ sampling is performed in
the first cycle only.
For example, in the case shown in figure 11.19, DMAC transfer begins, at the earliest, five
CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of
the number of data transfers set in DMATCR. DREQ is not sampled during this time, and
therefore DRAK is output in the first cycle only. In the case of dual address mode transfer
initiated by an external request, the DACK signal can be output in either the read cycle or the
write cycle of the DMAC transfer according to the specification of the AM bit in CHCR.
In burst mode using single address mode and edge detection, DREQ sampling is performed
only in the first cycle.
For example, in the case shown in figure 11.27, DMAC transfer begins, at the earliest, five
cycles after the first sampling operation. DMAC transfer then continues until the end of the
number of data transfers set in DMATCR. DREQ is not sampled during this time, and
therefore DRAK is output in the first cycle only.
In single address mode, the DACK signal is output every DMAC transfer cycle.
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