D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 702
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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D17760BP200AD
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3. The SCIF checks the SCFTDR transmit data at the timing for sending the last bit. If data is
4. After serial transmission ends, the SCIF_CLK pin is fixed high.
Figure 17.18 shows an example of the operation for transmission in synchronous mode.
Rev. 2.00 Feb. 12, 2010 Page 618 of 1330
REJ09B0554-0200
SCFCR, the TDFE flag is set. If the TIE bit in SCSCR is set to 1 at this time, a transmit-FIFO-
data-empty interrupt (TXI) request is generated.
If clock output mode is selected, the SCIF outputs eight synchronization clock pulses for each
data.
When the external clock is selected, data is output in synchronization with the input clock.
The serial transmit data is sent from the SCIF_TXD pin in the LSB-first order.
present, the data is transferred from SCFTDR to SCTSR, and then serial transmission of the
next frame is started. If there is no transmit data, the TEND flag in SCFSR is set to 1 after the
last bit is sent, and the transmit data pin (SCIF_TXD pin) retains the output state of the last bit.
Synchronization
Figure 17.18 Sample SCIF Transmission Operation in Synchronous Mode
Serial data
TEND
TDFE
clock
interrupt
request
TXI
and TDFE flag cleared to 0
Bit 0
LSB
Data written to SCFTDR
by TXI interrupt handler
Bit 1
One frame
TXI interrupt
MSB
Bit 7
request
Bit 0
Bit 1
Bit 6
Bit 7
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