D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 740
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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In T = 0 mode, if an error signal is received during transmission, the disputed data is automatically
repeated. This repetition generates no DMA transfer request, so it is possible to transmit the
number of bytes assigned to the DMAC.
For error handling with an interruput request to the CPU in transmission using the DMAC, set the
TIE bit to 0 to disable an SIMTXI request, and set the RIE bit to 1 to enable an SIMERI request.
Clear the ERS flag by sending an interrupt request to the CPU since it is not automatically cleared
once set when an error signal was received.
The receiver issues a receive data full DMA transfer request when the RDRF flag in SISSR is set
to 1. It is possible to start the DMAC to transfer data with a receive data full DMA transfer request
by setting this request as a DMAC startup factor in advance.
In T = 0 mode, if a parity error occurs during reception, a data repeat request is issued. Since the
RDRF flag is not set and a DMA transfer request is not issued, it is possible to receive the number
of bytes assigned to the DMAC.
For error handling with an interrupt to the CPU in reception using the DMAC, set the RIE and
EIO bits to 1 to disable an SIMRXI interrupt and to enable only an SIMERI request.
Clear the PER, ORER, and WAIT_ER flags by sending an interrupt request to the CPU since they
are not automatically cleared once set by a receive error.
For transmission/reception using the DMAC, the DMAC should be configured to be enabled
before configuring the smart card interface.
18.5
The following matters should be noted when using the smart card interface.
18.5.1
When the SISMPL register holds its initial value, the smart card interface operates at a serial clock
frequency (SIM_CLK) 372 times the transfer rate.
During reception, the smart card interface samples the falling edge of the start bit using the serial
SIM_CLK for internal synchronization. Received data is captured internally at the center of one
etu (at the rising edge of the 186th SIM_CLK pulse when one etu takes 372 SIM_CLK cycles).
This is shown in figure 18.7.
Rev. 2.00 Feb. 12, 2010 Page 656 of 1330
REJ09B0554-0200
Usage Notes
Receive data Timing
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