D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 1119
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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D17760BP200AD
Manufacturer:
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Quantity:
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28.3.3
SDINT is a 16-bit register that can be read from/written to by the CPU. Specifying an H-UDI
interrupt command in SDIR via H-UDI pin (Update-IR) sets the INTREQ bit to 1. While SDIR
contains an H-UDI interrupt command, SDINT is connected between the TDI and TDO pins.
SDINT can be read as a 32-bit register; the upper 16 bits will be 0 and the lower 16 bits represent
the SDINT register.
The CPU can write 0 alone to the INTREQ bit. As long as this bit is set to 1, an interrupt request
will continue to be generated. Therefore, the INTREQ bit must be cleared to 0 during the interrupt
handler. The SDINT register is initialized when TRST is driven low or the TAP controller enters
the Test-Logic-Reset state.
Initial value:
Bit
15 to 1 —
0
R/W:
Bit:
Bit Name Initial Value
INTREQ
Interrupt Source Register (SDINT)
15
-
R
0
14
R
0
-
All 0
0
13
R
0
-
12
R
0
-
11
R
0
-
R/W
R
R/W
10
R
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Interrupt Request
Indicates whether or not an interrupt request by an H-
UDI interrupt command has occurred. Clearing this bit
to 0 by the CPU cancels an interrupt request. Writing 1
to this bit retains the previous value.
R
9
0
-
R
8
0
-
R
7
0
-
Rev. 2.00 Feb. 12, 2010 Page 1035 of 1330
-
6
0
R
5
0
R
-
4
0
R
-
3
0
R
-
REJ09B0554-0200
2
0
R
-
1
-
0
R
INTREQ
R/W
0
0
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