D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 836
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number:
D17760BP200AD
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
D17760BP200ADV
Manufacturer:
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21.3.3
HcCommandStatus indicates the current status of HC. HC reads this register to receive a
command issued by HCD. HCD sets each bit by writing 1 and HC clears it by writing 0.
Initial value:
Initial value:
Bits
31 to
18
17
16
15 to 4
3
Rev. 2.00 Feb. 12, 2010 Page 752 of 1330
REJ09B0554-0200
R/W:
R/W:
Bit:
Bit:
Command Status Register (HcCommandStatus)
Bit Name
⎯
SOC1
SOC0
⎯
OCR
31
15
R
R
0
0
-
-
30
14
-
R
-
R
0
0
29
13
R
R
0
0
-
-
Initial Value
All 0
0
0
All 0
0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
R/W
R
R
R
R
R/W
26
10
R
R
-
0
-
0
25
R
R
-
0
9
-
0
Description
Reserved
These bits are always read as 0. Always write 0 to
these bits.
Scheduling Overrun Count
These bits are incremented in each
SchedulingOverrun error. These bits are initialized to
B'00 and wrap around at B'11. These bits are
incremented when scheduling overrun is detected
even though the SO bit in HcInterruptStatus is set.
These bits are used by HCD to monitor any
persistent scheduling problem.
Reserved
These bits are always read as 0. Always write 0 to
these bits.
Ownership Change Request
This bit is set to 1 by OS HCD to request a change of
control of HC. When this bit is1, HC sets the OC bit
in the HcInterruptStatus. After a change, this bit is
cleared to 0 and remains 0 until the next request
from OS HCD.
0: Do not request the change of the control of HC
1: Request the change of the control of HC
24
R
R
0
8
0
-
-
23
R
R
0
7
0
-
-
22
R
R
0
0
6
-
-
21
R
R
0
5
0
-
-
20
R
R
0
4
0
-
-
OCR
R/W
19
R
0
3
0
-
BLF
R/W
18
R
0
2
0
-
SOC1 SOC0
CLF
R/W
17
R
0
1
0
HCR
R/W
16
R
0
0
0
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