D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 1162
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Part Number:
D17760BP200AD
Manufacturer:
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30.3.8
LDPALCR selects whether the CPU or LCDC accesses the palette memory. When the palette
memory is being used for display operation, display mode should be selected. When the palette
memory is being written to, color-palette setting mode should be selected.
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 1078 of 1330
REJ09B0554-0200
Bit
15 to 5
4
3 to 1
0
R/W:
Bit:
LCDC Palette Control Register (LDPALCR)
Bit Name
⎯
PALS
⎯
PALEN
15
R
0
-
14
R
-
0
13
Initial Value
All 0
0
All 0
0
R
0
-
12
R
0
-
11
R
0
-
R/W
R
R
R
R/W
10
R
0
-
R
9
0
Description
Reserved
These bits always read as 0. The write value should
always be 0.
Palette State
Indicates the access right state of the palette.
0: Display mode: LCDC uses the palette
1: Color-palette setting mode: The host (CPU)
Reserved
These bits are always read as 0. The write value
should always be 0.
Palette Read/Write Enable
Requests the access right to the palette.
0: Request for transition to normal display mode
1: Request for transition to color palette setting mode
-
uses the palette
R
8
0
-
7
0
R
-
0
R
6
-
R
5
0
-
PALS
4
0
R
R
3
0
-
R
2
0
-
R
1
0
-
PALEN
R/W
0
0
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