D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 294
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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(11) General FPU Disable Exception
• Source: Decoding of an FPU instruction* not in a delay slot with SR.FD =1
• Transition address: VBR + H'0000 0100
• Transition operations:
Note: * FPU instructions are instructions in which the first 4 bits of the instruction code are F
Rev. 2.00 Feb. 12, 2010 Page 210 of 1330
REJ09B0554-0200
General_fpu_disable_exception()
{
}
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'800 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0100.
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'0000 0800;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0100;
(but excluding undefined instruction H'FFFD), and the LDS, STS, LDS.L, and STS.L
instructions corresponding to FPUL and FPSCR.
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