D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 432

• Manufacturer Part Number: D17760BP200AD
• Description: IC SUPERH MPU ROMLESS 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of D17760BP200AD

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 69
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

10.6.6
In this LSI, setting the A56PCM bit in BCR1 to 1 allows the bus interface for off-chip memory
space areas 5 and 6 to become an IC memory card interface or I/O card interface as stipulated in
JEIDA specification version 4.2 (PCMCIA2.1).
Figure 10.36 shows an example of PCMCIA card connection to this LSI. To enable hot swapping
of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a tri-state
buffer must be connected between this LSI bus interface and the PCMCIA cards.
Since operation in big endian mode is not explicitly stipulated in the JEIDA/PCMCIA standard,
this LSI supports only little-endian mode setting and the little-endian mode PCMCIA interface.
When the MMU is on, PCMCIA interface memory space can be set in MMU page units, and there
is a choice of 8-bit shared memory, 16-bit shared memory, 8-bit attribute memory, 16-bit attribute
memory, 8-bit I/O space, 16-bit I/O space, or dynamic bus sizing. See section 6, Memory
Management Unit (MMU), for details of the setting method. When the MMU is off, the memory
space is always used for access in the setting of bits SA2 to SA0 in PTEA.
Rev. 2.00 Feb. 12, 2010 Page 348 of 1330
REJ09B0554-0200
CKIO
A25–A5
A4–A0
CSn
RD/WR
RD
D31–D0
(read)
BS
RDY
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
PCMCIA Interface
TS1
Figure 10.35 Burst ROM Wait Access Timing
T1
TB2 TH1 TS1 TB1 TB2
TH1
TS1
TB1
TB2
TH1 TS1 TB1
T2
TH1