D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 584
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Part Number:
D17760BP200AD
Manufacturer:
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• Turning On PLL Circuit 3
• Turning Off PLL Circuit 3
12.5.7
Before changing the DCK clock frequency division ratio, be sure to stop oscillation of PLL circuit
3.
1. Clear the PLL3EN bit in DCKDR to 0. Then set the clock frequency division ratio with the
2. Set the PLL3EN bit to 1.
3. The on-chip fixed timer starts counting up. At this time, an unstable clock is output to the DCK
4. After the on-chip fixed timer finishes counting, the DCKEN bit is set to 1 to indicate that DCK
12.5.8
The DCK pin can be switched between clock output and the high-impedance state by means of the
DCKOUT bit in DCKDR. When the DCK pin goes to the high-impedance state, it is pulled up.
Make the DCKOUT bit setting after stopping PLL circuit 3.
1.
Rev. 2.00 Feb. 12, 2010 Page 500 of 1330
REJ09B0554-0200
1. Set the PLL3EN bit in DCKDR to 1.
2. The on-chip fixed timer starts counting up. At this time, an unstable clock is output to the
3. After the on-chip fixed timer finishes counting, the DCKEN bit is set to 1 to indicate that
1. Clear the PLL3EN bit in DCKDR to 0.
DIV0 and DIV1 bits in DCKDR.
pin. The DCKEN bit is cleared to 0 to indicate that the DCK cannot be used.
oscillation has become stable.
Clear the PLL3EN bit in DCKDR to 0. Then set the DCK pin state with the DCKOUT bit.
DCK pin. The DCKEN bit is cleared to 0 to indicate that the DCK cannot be used.
DCK oscillation has become stable. For the time until the on-chip fixed timer finishes
counting (oscillation stabilization time), refer to section 33, Electrical Characteristics.
Changing DCK Output Clock Division Ratio
Controlling DCK Output Clock
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