D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 774
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Section 19 I
when the byte count in ICTXD exceeds the transmit trigger byte count. The transmit byte count in
ICTXD can be informed by ICTFDR.
(6) Reading from ICRXD and the RDF Flag (FIFO Buffer Mode)
The RDF flag of ICFSR is set to 1 when the receive byte count in ICRXD reaches the receive
trigger byte count by RTRG3 to RTRG0 bits of ICFCR. After RDF is set, the receive data for the
trigger byte count can be read from ICRXD. This allows efficient continuous reception.
When the byte count in ICRXD is equivalent to or greater than the trigger count after a read, the
RDF flag is cleared to 0 even if it is set to 1 again. Accordingly, read the RDF flag as 1 and then
clear it to 0 after reading all data. The receive byte count in ICRXD can be informed by ICRFDR.
19.4.5
Figure 19.2 shows the bus timing of the I
19.2.
Table 19.4 Legend in I
Rev. 2.00 Feb. 12, 2010 Page 690 of 1330
REJ09B0554-0200
Symbol
S
SLA
R/W
A
DATA
P
I
SDA
SCL
2
C Bus Data Format
2
C Bus Interface
Description
is high level.
Indicates the direction of data transfer: from the slave device to the master
device when R/W is 1, or from the master device to the slave device when
R/W is 0.
device returns a data acknowledge signal in master transmit mode.
is high level.
Start condition. The master device drives SDA from high to low level while SCL
Slave address. The slave address is selected by the master device.
Data acknowledge. Data receive device drives SDA to low level. The slave
Transfer data. The data consists of 8 bits, which are transferred from MSB.
Stop condition. The master device drives SDA from low to high level while SCL
S
SLA
2
1–7
C Bus Data Format
R/W
8
Figure 19.2 I
9
A
2
C bus interface. Table 19.4 describes legend in figure
1–7
DATA
2
C Bus Timing
8
9
A
1–7
DATA
8
A/A
9
P
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