D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 242
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Price
Company:
Part Number:
D17760BP200AD
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Part Number:
D17760BP200ADV
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7.2.2
QACR0 can be accessed in longwords from H'FF00 0038 in the P4 area and from H'1F00 0038 in
area 7. QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is
off.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 158 of 1330
REJ09B0554-0200
Bit
1
0
Bit
31 to 5
4 to 2
1, 0
R/W:
R/W:
Bit:
Bit:
Queue Address Control Register 0 (QACR0)
AREA0
Bit Name
WT
OCE
Bit Name
⎯
⎯
31
15
R
R
-
-
-
-
30
14
R
R
-
-
-
-
29
13
R
R
-
-
-
-
Initial Value
0
0
Initial Value
⎯
⎯
⎯
28
12
R
R
-
-
-
-
27
11
R
R
-
-
-
-
26
10
R
R
-
-
-
-
R/W
R/W
R/W
R/W
R
R/W
R
25
R
R
9
-
-
-
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
When the MMU is off, these bits generate external
address bits [28:26] for SQ0.
Reserved
These bits are always read as 0. The write value
should always be 0.
Description
Write-Through Mode
Indicates the P0, U0, and P3 area cache write
mode. When address translation is performed,
the value of the WT bit in the page management
information has priority.
0: Copy-back mode
1: Write-through mode
OC Enable Bit
Selects whether the OC is used. Note however
when address translation is performed, the OC
cannot be used unless the C bit in the page
management information is also 1.
0: OC not used
1: OC used
24
R
R
8
-
-
-
-
23
R
R
7
-
-
-
-
22
R
R
6
-
-
-
-
21
R
R
5
-
-
-
-
R/W
20
R
4
-
-
-
AREA0
R/W
19
R
-
-
3
-
R/W
18
R
2
-
-
-
17
R
R
-
-
1
-
-
16
R
R
0
-
-
-
-
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