D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 454
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Price
Company:
Part Number:
D17760BP200AD
Manufacturer:
Renesas Electronics America
Quantity:
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D17760BP200ADV
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32-byte transfer is performed consecutively for a total of 32 bytes according to the bus width that
was set. The first access is performed on the data where there was an access request. The
remaining accesses are performed on the 32-byte boundary data in wraparound mode. The bus is
not released during this operation.
Figure 10.56 shows an example of a byte control SRAM connection, and figures 10.57 to 10.59
show examples of byte control SRAM read cycles.
Rev. 2.00 Feb. 12, 2010 Page 370 of 1330
REJ09B0554-0200
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.56 Example of 32-Bit Data Width Byte Control SRAM
SH7760
D31 − D16
D15 − D0
A18 − A3
RD/WR
WE3
WE2
WE1
WE0
CSn
RD
64k × 16-bit
A15 − A0
CS
OE
WE
I/O15 − I/O0
UB
LB
A15 − A0
CS
OE
WE
I/O15 − I/O0
UB
LB
SRAM
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