D17760BP200AD Renesas Electronics America, D17760BP200AD Datasheet - Page 633
D17760BP200AD
Manufacturer Part Number
D17760BP200AD
Description
IC SUPERH MPU ROMLESS 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D17760BP200AD
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
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Quantity
Price
Company:
Part Number:
D17760BP200AD
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
D17760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
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Table 16.2 Register Configuration (2)
Ch.
Common
0
1
2
3
Note: * After exiting hardware standby mode, this LSI enters the power-on reset state caused by
Channel 3 time register
Channel 3 stop time register
Channel 3
Register Name
Configuration register
Free-running timer
Control register
IRQ status register
Channel 0 time register
Channel 0 stop time register
Channel 0
Channel 1 time register
Channel 1 stop time register
Channel 1
Channel 2 time register
Channel 2 stop time register
Channel 2
the RESET pin.
timer/
timer/
timer/
timer/
counter
counter
counter
counter
CMTCH3C H'0000 0000 H'0000 0000
Abbrev.
CMTCFG
CMTFRT
CMTCTL
CMTIRQS H'0000 0000 H'0000 0000
CMTCH0T H'0000 0000 H'0000 0000
CMTCH0ST H'0000 0000 H'0000 0000
CMTCH0C H'0000 0000 H'0000 0000
CMTCH1T H'0000 0000 H'0000 0000
CMTCH1ST H'0000 0000 H'0000 0000
CMTCH1C H'0000 0000 H'0000 0000
CMTCH2T H'0000 0000 H'0000 0000
CMTCH2ST H'0000 0000 H'0000 0000
CMTCH2C H'0000 0000 H'0000 0000
CMTCH3T H'0000 0000 H'0000 0000
CMTCH3ST H'0000 0000 H'0000 0000
Power-on
Reset by
RESET
Pin/WDT/
H-UDI
H'0000 0000 H'0000 0000
H'0000 0000 H'0000 0000
H'0000 0000 H'0000 0000
Manual Reset
by RESET
Pin/WDT/
Multiple
Exception
Rev. 2.00 Feb. 12, 2010 Page 549 of 1330
Retained
Retained
Retained
Sleep
by Sleep
Instruction/
Deep Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
by
Hardware
REJ09B0554-0200
*
Standby
Retained
Retained
Retained
by
Software/
Each
Module
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
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