DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 790
DF3048BVX25V
Manufacturer Part Number
DF3048BVX25V
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048BVX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048BVX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Appendix B Internal I/O Register
DTCR0B—Data Transfer Control Register 0B (cont)
Rev. 3.00 Sep 27, 2006 page 762 of 872
REJ09B0325-0300
Full address mode
Data transfer master enable
Bit
Initial value
Read/Write
0 Data transfer is disabled
1 Data transfer is enabled
Destination address increment/decrement (bit 5)
Destination address increment/decrement enable (bit 4)
DAID
Bit 5
0
1
Transfer mode select
0 Destination is the block area in block transfer mode
1 Source is the block area in block transfer mode
Data transfer select 2B to 0B
DTS2B
DAIDE
Bit 4
Bit 2
0
1
0
1
0
1
DTME
R/W
DTS1B
Increment/Decrement Enable
MARB is held fixed
Incremented:
MARB is held fixed
Decremented:
Bit 1
7
0
0
1
0
1
DTS0B
Bit 0
R/W
0
1
0
1
0
1
0
1
6
0
If DTSZ = 0, MARB is incremented by 1 after each transfer
If DTSZ = 1, MARB is incremented by 2 after each transfer
If DTSZ = 0, MARB is decremented by 1 after each transfer
If DTSZ = 1, MARB is decremented by 2 after each transfer
Normal Mode
Auto-request
(burst mode)
Not available
Auto-request
(cycle-steal mode)
Not available
Not available
Not available
Falling edge of
Low level input at
DAID
R/W
5
0
Data Transfer Activation Source
DAIDE
R/W
DREQ
4
0
DREQ
TMS
R/W
3
0
Block Transfer Mode
Compare match/input capture
A from ITU channel 0
Compare match/input capture
A from ITU channel 1
Compare match/input capture
A from ITU channel 2
Compare match/input capture
A from ITU channel 3
Not available
Not available
Falling edge of
Not available
DTS2B
H'2F
R/W
2
0
DTS1B
DREQ
R/W
1
0
DTS0B
R/W
DMAC0
0
0
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