DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 34
DF3048BVX25V
Manufacturer Part Number
DF3048BVX25V
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048BVX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048BVX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 1 Overview
1.2
Figure 1.1 shows an internal block diagram.
Rev. 3.00 Sep 27, 2006 page 6 of 872
REJ09B0325-0300
Notes: 1. This pin functions as the FWE (input) pin on the H8/3048F-ONE (single power supply on-chip flash memory version). On
P8
2. Pin 1 on the H8/3048B Group which operates at 5 V is not used as the V
Block Diagram
RESO/FWE
P8
P8
P8
0
/RFSH/IRQ
3
2
1
P6
P6
/CS
/CS
/CS
H8/300H Series versions with on-chip mask ROM it functions as the RESO (output) pin, and on dual power supply flash
memory versions (V
external capacitor must be connected. Pin 1 is the V
P6
P6
P6
P8
1
P6
2
P6
0
5
/BREQ
EXTAL
/BACK
1
2
3
6
/WAIT
STBY
/HWR
4
/LWR
/IRQ
/IRQ
/IRQ
XTAL
4
/CS
MD
MD
MD
RES
3
NMI
/RD
/AS
*1
2
1
0
0
3
2
1
0
PP
Port B
= 12 V) and on-chip PROM versions it functions as the RESO (output)/V
Figure 1.1 Block Diagram
Interrupt controller
16-bit integrated
controller (TPC)
Programmable
timing pattern
(mask ROM,
timer unit
memory)
or flash
ROM
RAM
(ITU)
Port A
H8/300H CPU
CC
pin on versions that operate on 3 V.
Port 3
DMA controller
Serial communication
(SCI)
controller
(DMAC)
Refresh
Watchdog timer
A/D converter
D/A converter
Address bus
Data bus (upper)
Data bus (lower)
interface
(WDT)
2 channels
CC
terminal, but is used as the V
Port 4
Port 7
PP
(input) pin.
P5
P5
P5
P5
P2
P2
P2
P2
P2
P2
P2
P2
P1
P1
P1
P1
P1
P1
P1
P1
P9
P9
P9
P9
P9
P9
CL
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
5
4
3
2
1
0
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/A
/SCK
/SCK
/RxD
/RxD
/TxD
/TxD
terminal; the
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
0
1
0
1
0
/IRQ
/IRQ
5
4
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