DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 559
DF3048BVX25V
Manufacturer Part Number
DF3048BVX25V
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048BVX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048BVX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 559 of 903
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Section 14 Smart Card Interface
Transmitting Serial Data
The transmitting procedure in smart card mode is different from the normal SCI procedure,
because of the need to sample the error signal and retransmit. Figure 14.4 shows a flowchart for
transmitting, and figure 14.5 shows the relation between a transmit operation and the internal
registers.
1. Initialize the smart card interface by the procedure given above in Initialization.
2. Check that the ERS error flag is cleared to 0 in SSR.
3. Check that the TEND flag is set to 1 in SSR. Repeat steps 2 and 3 until this check passes.
4. Write transmit data in TDR and clear the TDRE flag to 0. The data will be transmitted and the
TEND flag will be cleared to 0.
5. To continue transmitting data, return to step 2.
6. To terminate transmission, clear the TE bit to 0.
This procedure may include interrupt handling and DMA transfer.
If the TIE bit is set to 1 to enable interrupt requests, when transmission is completed and the
TEND flag is set to 1, a transmit-data-empty interrupt (TXI) is requested. If the RIE bit is set to 1
to enable interrupt requests, when a transmit error occurs and the ERS flag is set to 1, a
transmit/receive-error interrupt (ERI) is requested.
The timing of TEND flag setting depends on the GM bit in SMR. The timing is shown in figure
14.6.
If the TXI interrupt activates the DMAC, the number of bytes designated in the DMAC can be
transmitted automatically, including automatic retransmit.
For details, see Interrupt Operations and Data Transfer by DMAC in this section.
Rev. 3.00 Sep 27, 2006 page 531 of 872
REJ09B0325-0300
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