DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 490

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface
Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data length in asynchronous mode. In
synchronous mode the data length is 8 bits regardless of the CHR setting.
Bit 6: CHR
0
1
Note:
Bit 5—Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a
parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode
the parity bit is neither added nor checked, regardless of the PE setting.
Bit 5: PE
0
1
Note:
Bit 4—Parity Mode (O/E E E E ): Selects even or odd parity. The O/E bit setting is valid in
asynchronous mode when the PE bit is set to 1 to enable the adding and checking of a parity bit.
The O/E setting is ignored in synchronous mode, or when parity adding and checking is disabled
in asynchronous mode.
Bit 4: O/E E E E
0
1
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even
Rev. 3.00 Sep 27, 2006 page 462 of 872
REJ09B0325-0300
* When 7-bit data is selected, the MSB (bit 7) in TDR is not transmitted.
* When PE is set to 1, an even or odd parity bit is added to transmit data according to the
2. When odd parity is selected, the parity bit added to transmit data makes an odd number
even or odd parity mode selected by the O/E bit, and the parity bit in receive data is
checked to see that it matches the even or odd mode selected by the O/E bit.
number of 1s in the transmitted character and parity bit combined. Receive data must
have an even number of 1s in the received character and parity bit combined.
of 1s in the transmitted character and parity bit combined. Receive data must have an
odd number of 1s in the received character and parity bit combined.
Description
8-bit data
7-bit data *
Description
Parity bit not added or checked
Parity bit added and checked *
Description
Even parity *
Odd parity *
2
1
(Initial value)
(Initial value)
(Initial value)