DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 242
DF3048BVX25V
Manufacturer Part Number
DF3048BVX25V
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048BVX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048BVX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 8 DMA Controller
8.3.4
The data transfer control registers (DTCRs) are 8-bit readable/writable registers that control the
operation of the DMAC channels. A channel operates in full address mode when bits DTS2A and
DTS1A are both set to 1 in DTCRA. DTCRA and DTCRB have different functions in full address
mode.
DTCRA
DTCRA is initialized to H'00 by a reset and in standby mode.
Bit 7—Data Transfer Enable (DTE): Together with the DTME bit in DTCRB, this bit enables
or disables data transfer on the channel. When the DTME and DTE bits are both set to 1, the
channel is enabled. If auto-request is specified, data transfer begins immediately. Otherwise, the
channel waits for transfers to be requested. When the specified number of transfers have been
completed, the DTE bit is automatically cleared to 0. When DTE is 0, the channel is disabled and
does not accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then
writing 1.
Rev. 3.00 Sep 27, 2006 page 214 of 872
REJ09B0325-0300
Bit
Initial value
Read/Write
Data transfer enable
Enables or disables
data transfer
Data Transfer Control Registers (DTCR)
DTE
R/W
7
0
Data transfer size
Selects byte or
word size
DTSZ
R/W
6
0
Source address
increment/decrement
Source address increment/
decrement enable
These bits select whether
the source address register
(MARA) is incremented,
decremented, or held fixed
during the data transfer
SAID
R/W
5
0
SAIDE
R/W
Data transfer
interrupt enable
Enables or disables the
CPU interrupt at the end
of the transfer
4
0
DTIE
R/W
3
0
DTS2A
R/W
Data transfer select
2A and 1A
These bits must both be
set to 1
2
0
DTS1A
R/W
1
0
Data transfer
select 0A
Selects block
transfer mode
DTS0A
R/W
0
0
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