DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 662

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 Clock Pulse Generator
External Clock
The external clock frequency should be equal to the system clock frequency ( ) when not divided
by the on-chip frequency divider. Table 19.4, figures 19.6 and 19.7 indicate the clock timing.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (t
must remain reset with the reset signal low during t
Table 19.4(1) Clock Timing for H8/3048B Group (8 MHz
Item
External clock input low
pulse width
External clock input high
pulse width
External clock rise time
External clock fall time
Clock low pulse width
Clock high pulse width
External clock output
settling delay time
Note:
Rev. 3.00 Sep 27, 2006 page 634 of 872
REJ09B0325-0300
* t
DEXT
includes a RES pulse width (t
Symbol Min
t
t
t
t
t
t
t
EXL
EXH
EXr
EXf
CL
CH
DEXT
*
t
t
—
—
0.4
0.4
500
cyc
cyc
3.0 V to 3.6 V
/2–5
/2–5
V
RESW
CC
DEXT
Max
—
—
5
5
0.6
0.6
—
=
). t
) has passed after the clock input. The system
RESW
DEXT
, while the clock output is unstable.
= 20 t
Min
t
t
—
—
0.4
0.4
500
cyc
cyc
cyc
/2–5
/2–5
5.0 V ±10%
f
V
CC
25 MHz)
Max
—
—
5
5
0.6
0.6
—
=
Unit
ns
ns
ns
ns
t
t
µs
cyc
cyc
Test
Conditions
Figure 19.6
Figure 19.7
Figure 21.7