DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 225
DF3048BVX25V
Manufacturer Part Number
DF3048BVX25V
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048BVX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048BVX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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If a bus cycle is prolonged by insertion of wait states, the first refresh request is held, as in the
bus-released state.
If there is contention with a bus request from an external bus master when making a transition
to software standby mode, a one-state bus-released state may occur immediately before the
transition to software standby mode (see figure 7.25).
When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the
SLEEP instruction.
When making a transition to self-refresh mode, the strobe waveform output may not be
guaranteed due to the same kind of contention. This, too, can be prevented by clearing the
BRLE bit to 0 in BRCR.
BREQ
BACK
Address bus
Strobe
Figure 7.25 Contention between Bus-Released State and Software Standby Mode
RFSH
Refresh
request
BACK
Bus-released state
Figure 7.24 Refresh Cycles when Bus Is Released
External bus
released state
Refresh cycle
Software standby mode
Rev. 3.00 Sep 27, 2006 page 197 of 872
CPU cycle
Section 7 Refresh Controller
Refresh cycle
REJ09B0325-0300
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