DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 236
DF3048BVX25V
Manufacturer Part Number
DF3048BVX25V
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048BVX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number
Manufacturer
Quantity
Price
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Part Number:
DF3048BVX25V
Manufacturer:
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Quantity:
10 000
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Section 8 DMA Controller
8.2.4
A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the
operation of one DMAC channel.
The DTCRs are initialized to H'00 by a reset and in standby mode.
Bit 7—Data Transfer Enable (DTE): Enables or disables data transfer on a channel. When the
DTE bit is set to 1, the channel waits for a transfer to be requested, and executes the transfer when
activated as specified by bits DTS2 to DTS0. When DTE is 0, the channel is disabled and does not
accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1.
Bit 7: DTE
0
1
If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.
Rev. 3.00 Sep 27, 2006 page 208 of 872
REJ09B0325-0300
Bit
Initial value
Read/Write
Data transfer enable
Enables or disables
data transfer
Data Transfer Control Registers (DTCR)
DTE
R/W
Description
Data transfer is disabled. In I/O mode or idle mode, DTE is cleared to 0 when
the specified number of transfers have been completed.
Data transfer is enabled
7
0
Data transfer size
Selects byte or
word size
Data transfer
increment/decrement
Selects whether to
increment or decrement
the memory address
register
DTSZ
R/W
6
0
DTID
R/W
5
0
Repeat enable
Selects repeat
mode
RPE
R/W
4
0
Data transfer interrupt enable
Enables or disables the CPU interrupt
at the end of the transfer
DTIE
R/W
3
0
DTS2
R/W
2
0
Data transfer select
These bits select the data
transfer activation source
DTS1
R/W
1
0
(Initial value)
DTS0
R/W
0
0
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