DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 206

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Refresh Controller
Operation in Power-Down State
The refresh controller operates in sleep mode. It does not operate in hardware standby mode. In
software standby mode RTCNT is initialized, but RFSHCR, RTMCSR bits 5 to 3, and RTCOR
retain their settings prior to the transition to software standby mode.
Example 1: Connection to 2WE
Figure 7.7 shows typical interconnections to a 2WE 1-Mbit DRAM, and the corresponding
address map. Figure 7.8 shows a setup procedure to be followed by a program for this example.
After power-up the DRAM must be refreshed to initialize its internal state. Initialization takes a
certain length of time, which can be measured by using an interrupt from another timer module, or
by counting the number of times RTMCSR bit 7 (CMF) is set. Note that no refresh cycle is
executed for the first refresh request after exit from the reset state or standby mode (the first time
the CMF flag is set; see figure 7.3). When using this example, check the DRAM device
characteristics carefully and use a procedure that fits them.
Rev. 3.00 Sep 27, 2006 page 178 of 872
REJ09B0325-0300
Figure 7.7 Interconnections and Address Map for 2WE
H8/3048B Group
H'60000
H'7FFFF
D
15
HWR
to D
LWR
WE
WE
WE 1-Mbit DRAM (1-Mbyte Mode)
CS
RD
A
A
A
A
A
A
A
A
8
7
6
5
4
3
2
1
3
0
DRAM area
a. Interconnections (example)
b. Address map
Area 3 (1-Mbyte mode)
WE
WE 1-Mbit DRAM (Example)
WE
A
A
A
A
A
A
A
A
RAS
CAS
UW
LW
OE
I/O
7
6
5
4
3
2
1
0
15
2WE 1-Mbit DRAM with
to I/O
16-bit organization
0