DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 498

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface
Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an
overrun error.
Bit 5: ORER
0
1
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its
Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing
error in asynchronous mode.
Bit 4: FER
0
1
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous
Rev. 3.00 Sep 27, 2006 page 470 of 872
REJ09B0325-0300
2. RDR continues to hold the receive data before the overrun error, so subsequent receive
2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not
previous value.
data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
value.
checked. When a framing error occurs the SCI transfers the receive data into RDR but
does not set the RDRF flag. Serial receiving cannot continue while the FER flag is set
to 1. In synchronous mode, serial transmitting is also disabled.
Description
Receiving is in progress or has ended normally
[Clearing conditions]
A receive overrun error occurred *
[Setting condition]
Reception of the next serial data ends when RDRF = 1.
Description
Receiving is in progress or has ended normally
[Clearing conditions]
A receive framing error occurred *
[Setting condition]
The stop bit at the end of receive data is checked and found to be 0.
The chip is reset or enters standby mode.
Software reads ORER while it is set to 1, then writes 0.
The chip is reset or enters standby mode.
Software reads FER while it is set to 1, then writes 0.
2
2
(Initial value) *
(Initial value) *
1
1