DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 566

• Manufacturer Part Number: DF3048BVX25V
• Description: MCU 3/5V 128K PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of DF3048BVX25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Smart Card Interface
Use the following procedure to secure the clock duty cycle after powering on.
1. The initial state is port input and high impedance. Use pull-up or pull-down resistors to fix the
2. Fix at the output specified by the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card interface mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
14.4
When using the SCI as a smart card interface, note the following points.
Receive Data Sampling Timing in Smart Card Mode and Receive Margin
In smart card mode the SCI operates on a base clock with 372 times the bit rate frequency. In
receiving, the SCI synchronizes internally with the fall of the start bit, which it samples on the
base clock. Receive data is latched at the rising edge of the 186th base clock pulse. See figure
14.10.
Rev. 3.00 Sep 27, 2006 page 538 of 872
REJ09B0325-0300
Internal
base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
potential.
Usage Notes
Figure 14.10 Receive Data Sampling Timing in Smart Card Mode
0
186 clocks
185
372 clocks
Start
bit
371
0
D0
185
371
0
D1