DF3048BVX25V Renesas Electronics America, DF3048BVX25V Datasheet - Page 640
DF3048BVX25V
Manufacturer Part Number
DF3048BVX25V
Description
MCU 3/5V 128K PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of DF3048BVX25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF3048BVX25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 18 ROM (H8/3048F-ONE: Single Power Supply, H8/3048B Mask ROM Version)
18.8.3
In error protection, an error is detected when H8/3048F-ONE runaway occurs during flash
memory programming/erasing *
program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
If the H8/3048F-ONE malfunctions during flash memory programming/erasing, the FLER bit is
set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2, EBR
settings *
occurred. Program mode or erase mode cannot be re-entered by re-setting the P, E bit. However,
PV, EV bit setting is enabled, and a transition can be made to verify mode *
FLER bit setting conditions are as follows:
1. When the flash memory of the relevant address area is read during programming/erasing
2. Immediately after exception handling (excluding an illegal reset or trap instruction and
3. When a SLEEP instruction (including software standby) is executed during
4. When the CPU releases the bus to the DMAC, refresh controller, and external bus master
Error protection is released only by a reset (RES pin or WDT reset) and in hardware standby
mode.
Notes: 1. State in which the P bit or E bit in FLMCR1 is set to 1. Note that NMI input is disabled
Rev. 3.00 Sep 27, 2006 page 612 of 872
REJ09B0325-0300
(including vector read and instruction fetch)
exception handling at zero division) during programming/erasing
programming/erasing
during programming/erasing
2. It is possible to perform a program-verify operation on the 128 bytes being
3. FLMCR1 and EBR can be written to. However, the registers are initialized if a
3
Error Protection
are retained, but program mode or erase mode is aborted at the point at which the error
in this state.
programmed, or an erase-verify on the block being erased.
transition is made to software standby mode while in the error-protected state.
1
, or operation is not performed in accordance with the
2
.
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