MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 90

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4
4.7.5 Interrupt Acknowledge Bus Cycles
4.8 Chip Selects
4-48
Interrupt acknowledge bus cycles are CPU32 space cycles that are generated during
exception processing. For further information about the types of interrupt acknowledge
bus cycles determined by AVEC or DSACK, refer to APPENDIX A ELECTRICAL
CHARACTERISTICS and the SIM Reference Manual (SIMRM/AD).
Typical microcontrollers require additional hardware to provide external select and ad-
dress decode signals. The MCU includes 12 programmable chip-select circuits that
can provide 2- to 20-clock-cycle access to external memory and peripherals. Address
block sizes of two Kbytes to one Mbyte can be selected. Figure 4-17 is a diagram of
a basic system that uses chip selects.
D. Modules that have requested interrupt service decode the priority value in AD-
E. After arbitration, the interrupt acknowledge cycle is completed in one of the fol-
F. The vector number is converted to a vector address.
G. The content of the vector address is loaded into the PC, and the processor
2. The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16]
3. The request level is latched from the address bus into the interrupt priority
DR[3:1]. If request priority is the same as acknowledged priority, arbitration by
IARB contention takes place.
lowing ways:
1. When there is no contention (IARB = %0000), the spurious interrupt moni-
2. The dominant interrupt source supplies a vector number and DSACK sig-
3. The AVEC signal is asserted (the signal can be asserted by the dominant
4. The bus monitor asserts BERR and the CPU32 generates the spurious in-
transfers control to the exception handler routine.
= %1111, which indicates that the cycle is an interrupt acknowledge CPU
space cycle; ADDR[15:4] = %111111111111; ADDR[3:1] = the priority of
the interrupt request being acknowledged; and ADDR0 = %1.
mask field in the status or condition code register.
tor asserts BERR, and the CPU generates the spurious interrupt vector
number.
nals appropriate to the access. The CPU acquires the vector number.
interrupt source or the pin can be tied low), and the CPU generates an au-
tovector number corresponding to interrupt priority.
terrupt vector number.
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MC68331