MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 147

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

6.3.5.4 Slave Wraparound Mode
6.3.6 Peripheral Chip Selects
MC68331
USER’S MANUAL
designated by BITS has been transferred, the QSPI stores the working queue pointer
value in CPTQP, increments the working queue pointer, and loads new transmit data
from transmit RAM into the data serializer. The working queue pointer address is used
the next time PCS0/SS is asserted, unless the CPU writes to NEWQP first.
The QSPI shifts one bit for each pulse of SCK until the slave select input goes high. If
SS goes high before the number of bits specified by the BITS field is transferred, the
QSPI resumes operation at the same pointer address the next time SS is asserted.
The maximum value that the BITS field can have is 16. If more than 16 bits are trans-
mitted before SS is negated, pointers are incremented and operation continues. The
QSPI transmits as many bits as it receives at each queue address, until the BITS value
is reached or SS is negated. SS does not need to go high between transfers as the
QSPI transfers data until reaching the end of the queue, whether SS remains low or is
toggled between transfers.
When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit
in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point,
the QSPI clears SPE and stops unless wraparound mode is enabled.
Slave wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can
wrap to pointer address $0 or to the address pointed to by NEWQP, depending on the
state of the WRTO bit in SPCR2. Slave wraparound operation is identical to master
wraparound operation.
Peripheral chip-select signals are used to select an external device for serial data
transfer. Chip-select signals are asserted when a command in the queue is executed.
Signals are asserted at a logic level corresponding to the value of the PCS bits in the
command. More than one chip-select signal can be asserted at a time, and more than
one external device can be connected to each PCS pin, provided proper fanout is ob-
served. PCS0 shares a pin with the slave select (SS) signal, which initiates slave mode
serial transfer. If SS is taken low when the QSPI is in master mode, a mode fault oc-
curs.
To set up a chip-select function, set the appropriate bit in PQSPAR, then configure the
chip-select pin as an output by setting the appropriate bit in DDRQS. The value of the
bit in PORTQS that corresponds to the chip-select pin determines the base state of
the chip-select signal. If base state is zero, chip-select assertion must be active high
(PCS bit in command RAM must be set); if base state is one, assertion must be active
low (PCS bit in command RAM must be cleared). PORTQS bits are cleared during re-
set. If no new data is written to PORTQS before pin assignment and configuration as
an output, base state of chip-select signals is zero and chip-select pins are configured
for active-high operation.
Freescale Semiconductor, Inc.
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