MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 215

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

D.2.7 PACTL — Pulse Accumulator Control Register
PAIS — PAI Pin State (Read Only)
PAEN — Pulse Accumulator Enable
PAMOD — Pulse Accumulator Mode
PEDGE — Pulse Accumulator Edge Control
PCLKS — PCLK Pin State (Read Only)
I4/O5 — Input Capture 4/Output Compare 5
PACLK[1:0] — Pulse Accumulator Clock Select (Gated Mode)
PACNT — Pulse Accumulator Counter
MC68331
USER’S MANUAL
RESET:
PAIS
15
U
PACTL enables the pulse accumulator and selects either event counting or gated
mode. In event counting mode, PACNT is incremented each time an event occurs. In
gated mode, it is incremented by an internal clock.
The effects of PEDGE and PAMOD are shown in the following table.
Eight-bit read/write counter used for external event counting or gated time accumula-
tion.
PACNT — Pulse Accumulator Counter
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
0 = External event counting
1 = Gated time accumulation
0 = Output compare 5 enabled
1 = Input capture 4 enabled
PAEN
14
0
PAMOD
13
0
PACLK[1:0]
PEDGE
PAMOD
12
0
00
01
10
11
Freescale Semiconductor, Inc.
0
0
1
1
For More Information On This Product,
PCLKS
11
U
Go to: www.freescale.com
I4/O5
REGISTER SUMMARY
10
0
PEDGE
0
1
0
1
9
0
PACLK
Same Clock Used to Increment TCNT
Pulse Accumulator Clock Selected
System Clock Divided by 512
PAI Falling Edge Increments Counter
8
0
PAI Rising Edge Increments Counter
External Clock, PCLK
TOF Flag from TCNT
Zero on PAI Inhibits Counting
One on PAI Inhibits Counting
7
0
0
Effect
0
0
PACNT
0
0
$YFF90C
$YFF90D
0
0
0
D-7
D