MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 114

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5
5.8.1 M68000 Family Compatibility
5.8.2 Special Control Instructions
5.8.2.1 Low Power Stop (LPSTOP)
5.8.2.2 Table Lookup and Interpolate (TBL)
5.9 Exception Processing
5-14
NOTE:
1. Privileged instruction
It is the philosophy of the M68000 family that all user-mode programs can execute un-
changed on a more advanced processor, and supervisor-mode programs and excep-
tion handlers should require only minimal alteration.
The CPU32 can be thought of as an intermediate member of the M68000 Family. Ob-
ject code from an MC68000 or MC68010 may be executed on the CPU32, and many
of the instruction and addressing mode extensions of the MC68020 are also support-
ed. Refer to the CPU32 reference manual for a detailed comparison of the CPU32 and
MC68020 instruction set.
Low power stop (LPSTOP) and table lookup and interpolate (TBL) instructions have
been added to the MC68000 instruction set for use in controller applications.
In applications where power consumption is a consideration, the CPU32 forces the de-
vice into a low power standby mode when immediate processing is not required. The
low power stop mode is entered by executing the LPSTOP instruction. The processor
remains in this mode until a user-specified (or higher) interrupt level or reset occurs.
To maximize throughput for real-time applications, reference data is often precalculat-
ed and stored in memory for quick access. Storage of many data points can require
an inordinate amount of memory. The table instruction requires that only a sample of
data points be stored, reducing memory requirements. The TBL instruction recovers
intermediate values using linear interpolation. Results can be rounded with a round-
to-nearest algorithm.
Exception processing is a special condition that preempts normal processing. Excep-
tion processing is the transition from normal mode program execution to execution of
a routine that deals with an exception.
Instruction
TRAPcc
TRAPV
UNLK
TST
Table 5-1 Instruction Set Summary (Continued)
#<data>
Syntax
<ea>
none
none
An
Freescale Semiconductor, Inc.
For More Information On This Product,
Operand Size
CENTRAL PROCESSING UNIT
8, 16, 32
Go to: www.freescale.com
16, 32
none
none
32
If V set, then overflow TRAP exception
An
Source – 0, to set condition codes
If cc true, then TRAP exception
SP; (SP)
Operation
An, SP + 4
USER’S MANUAL
SP
MC68331