MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 125

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5.10.4 On-Chip Breakpoint Hardware
5.11 Loop Mode Instruction Execution
MC68331
USER’S MANUAL
(IFETCH) output identifies the bus cycles in which the operand is loaded into the in-
struction pipeline. Pipeline flushes are also signaled with IFETCH. Monitoring these
two signals allows a bus analyzer to synchronize itself to the instruction stream and
monitor its activity.
An external breakpoint input and on-chip breakpoint hardware allow a breakpoint trap
on any memory access. Off-chip address comparators preclude breakpoints unless
show cycles are enabled. Breakpoints on instruction prefetches that are ultimately
flushed from the instruction pipeline are not acknowledged; operand breakpoints are
always acknowledged. Acknowledged breakpoints initiate exception processing at the
address in exception vector number 12, or alternately enter background mode.
The CPU32 has several features that provide efficient execution of program loops.
One of these features is the DBcc looping primitive instruction. To increase the perfor-
mance of the CPU32, a loop mode has been added to the processor. The loop mode
is used by any single word instruction that does not change the program flow. Loop
mode is implemented in conjunction with the DBcc instruction. Figure 5-12 shows the
required form of an instruction loop for the processor to enter loop mode.
The loop mode is entered when the DBcc instruction is executed, and the loop dis-
placement is –4. Once in loop mode, the processor performs only the data cycles as-
sociated with the instruction and suppresses all instruction fetches. The termination
condition and count are checked after each execution of the data operations of the
looped instruction. The CPU32 automatically exits the loop mode on interrupts or other
exceptions. All single word instructions that do not cause a change of flow can be
looped.
Figure 5-12 Loop Mode Instruction Sequence
Freescale Semiconductor, Inc.
For More Information On This Product,
ONE WORD INSTRUCTION
CENTRAL PROCESSING UNIT
DBCC DISPLACEMENT
Go to: www.freescale.com
$FFFC = – 4
DBCC
1126A
5-25
5