MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 71

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

MC68331
USER’S MANUAL
IF BREAKPOINT INSTRUCTION EXECUTED:
IF BKPT PIN ASSERTED:
IF BREAKPOINT INSTRUCTION EXECUTED AND
IF BKPT PIN ASSERTED AND
IF BERR ASSERTED:
IF BKPT INSTRUCTION EXECUTED:
IF BKPT PIN ASSERTED:
IF BKPT INSTRUCTION EXECUTED:
IF BKPT PIN ASSERTED:
DSACK IS ASSERTED:
DSACK IS ASSERTED:
1) PLACE LATCHED DATA IN INSTRUCTION PIPELINE
2) CONTINUE PROCESSING
1) CONTINUE PROCESSING
1) INITIATE ILLEGAL INSTRUCTION PROCESSING
1) INITIATE HARDWARE BREAKPOINT PROCESSING
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE BREAKPOINT NUMBER ON ADDR[4:2]
5) CLEAR T-BIT (ADDR1) TO ZERO
6) SET SIZE TO WORD
7) ASSERT AS AND DS
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE ALL ONES ON ADDR[4:2]
5) SET T-BIT (ADDR1) TO ONE
6) SET SIZE TO WORD
7) ASSERT AS AND DS
1) LATCH DATA
2) NEGATE AS AND DS
3) GO TO (A)
1) NEGATE AS AND DS
2) GO TO (A)
1) NEGATE AS AND DS
2) GO TO (B)
(A)
ACKNOWLEDGE BREAKPOINT
CPU32
Figure 4-12 Breakpoint Operation Flowchart
Freescale Semiconductor, Inc.
For More Information On This Product,
SYSTEM INTEGRATION MODULE
(B)
Go to: www.freescale.com
BREAKPOINT OPERATION FLOW
IF BKPT INSTRUCTION EXECUTED:
IF BKPT ASSERTED:
1) PLACE REPLACEMENT OPCODE ON DATA BUS
2) ASSERT DSACK
1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
1) ASSERT DSACK
1) ASSERT BERR TO INITIATE EXCEPTION PROCESSING
1) NEGATE DSACK OR BERR
OR:
OR:
PERIPHERAL
1110A
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