MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 112

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5
5-12
MOVE from CCR
MOVE from SR
MOVE to CCR
MOVE to SR
DIVSL/DIVUL
EORI to CCR
MOVE USP
MULS/MULU
EORI to SR
Instruction
LPSTOP
MOVEC
ILLEGAL
MOVEA
MOVES
MOVEM
MOVEQ
MOVEA
MOVEP
MOVE
NBCD
EXTB
EORI
LINK
EOR
EXG
EXT
JMP
LSR
JSR
LEA
LSL
1
1
1
1
1
1
1
1
# data , CCR
Dn, (d
(d
<ea>, Dh : Dl
# data
#<data>, Dn
# data , SR
# data Dn
# data Dn
ea , Dr : Dq
ea , Dr : Dq
CCR, ea
Table 5-1 Instruction Set Summary (Continued)
<ea>, SR
list, <ea>
<ea>, list
16
Rn, <ea>
<ea>, Rn
<ea>, Dn
USP, An
An, USP
ea , CCR
USP, An
An, USP
<ea>, Dl
SR, ea
Dn, ea
An, # d
ea , ea
Syntax
Rn, Rn
# data
Dn, Dn
Dn, Dn
ea , Dq
Rc, Rn
Rn, Rc
ea , An
ea , An
<ea>
none
, An), Dn
Dn
Dn
Dn
ea
ea
ea
ea
16
Freescale Semiconductor, Inc.
, An)
ea
For More Information On This Product,
64/32
32/32
Operand Size
16 * 16
32 * 32
32 * 32
CENTRAL PROCESSING UNIT
16, 32
16, 32
32/32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16
8
Go to: www.freescale.com
8
8
16, 32
16, 32
16, 32
none
none
none
none
16
32
32
16
16
32
32
16
16
16
16
32
32
32
32
8
8
8
32 : 32
32 : 32
16
32
32
32
32
32
32
32
32
64
Dn [31 : 24]
(An + d)
Dn [15 : 8]
(An + d + 4)
SP – 4
SP – 4
Data
Sign extended Destination
Sign extended Destination
SSP – 2
illegal instruction vector address
0 – Destination
Source
Source * Destination
Destination / Source
Data
Immediate data
SSP – 4
SSP – 2
Listed registers
SP, An
Rn
Dn [31 : 24]; (An + d + 2)
Source
Source using SFC
SR; interrupt mask
SP; PC
(An + d + 4); Dn [7 : 0]
Source
USP
(An + d); Dn [23 : 16]
Source
Source
Dn [15 : 8]; (An + d + 6)
(signed or unsigned)
(signed or unsigned)
Source
CCR
Rc
Destination
Destination
SR
SSP; vector offset
Destination
Source
Destination using DFC
Source
USP
An
Operation
Rn
ea
(SP); SP
SSP; PC
SSP; SR
10
RnRn
AnAn
Destination
Listed registers
CCR
Destination
(SP); destination
– X
Destination
Destination
SR
USP
Rn
An
An
CCR
SR
Destination
Destination
Destination
PC
Destination
Destination
CCR
SR
Destination
USP
Rc
Destination
An, SP + d
(SSP);
(SSP);
Destination
Destination
EBI; STOP
Rn
USER’S MANUAL
(SSP);
(An + d + 2);
Dn [23 : 16];
(An + d + 6)
PC
Dn [7 : 0]
PC
MC68331
SP