MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 119

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5.10.2.1 Enabling BDM
5.10.2.2 BDM Sources
MC68331
USER’S MANUAL
Accidentally entering BDM in a non-development environment can lock up the CPU32
when the serial command interface is not available. For this reason, BDM is enabled
during reset via the breakpoint (BKPT) signal.
BDM operation is enabled when BKPT is asserted (low), at the rising edge of RESET.
BDM remains enabled until the next system reset. A high BKPT signal on the trailing
edge of RESET disables BDM. BKPT is latched again on each rising transition of RE-
SET. BKPT is synchronized internally, and must be held low for at least two clock cy-
cles prior to negation of RESET.
BDM enable logic must be designed with special care. If hold time on BKPT extends
into the first bus cycle following reset, the bus cycle could inadvertently be tagged with
a breakpoint. Refer to the SIM Reference Manual (SIMRM/AD) for timing information.
When BDM is enabled, any of several sources can cause the transition from normal
mode to BDM. These sources include external breakpoint hardware, the BGND in-
struction, a double bus fault, and internal peripheral breakpoints. If BDM is not enabled
when an exception condition occurs, the exception is processed normally. Table 5-3
summarizes the processing of each source for both enabled and disabled cases. As
shown in Table 5-3, the BKPT instruction never causes a transition into BDM.
BGND Instruction
Double Bus Fault
BKPT Instruction
TARGET
SYSTEM
Source
BKPT
Figure 5-8 Bus State Analyzer Configuration
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5-3 BDM Source Summary
CENTRAL PROCESSING UNIT
TARGET
Go to: www.freescale.com
MCU
Opcode Substitution/
Illegal Instruction
BDM Enabled
Background
Background
Background
BUS STATE
ANALYZER
Breakpoint Exception
Opcode Substitution/
Illegal Instruction
Illegal Instruction
BDM Disabled
Halted
1129A
5-19
5