MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 225

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

LOC — Loss of Clock Reset
SYS — System Reset
TST — Test Submodule Reset
D.3.5 SIMTRE — System Integration Test Register (ECLK)
D.3.6 PORTE0/PORTE1 — Port E Data Register
D.3.7 DDRE — Port E Data Direction Register
D.3.8 PEPAR — Port E Pin Assignment Register
MC68331
USER’S MANUAL
15
RESET:
15
15
Reset caused by loss of clock frequency reference.
Reset caused by a RESET instruction.
Reset caused by the test submodule. Used during system test only.
Register is used for factory test only.
PORTE is an internal data latch that can be accessed at two locations. PORTE can be
read or written at any time. If a pin in I/O port E is configured as an output, the corre-
sponding bit value is driven out on the pin. When a pin is configured for output, a read
of PORTE returns the latched bit value; when a pin is configured for input, a read re-
turns the pin logic level.
Bits in this register control the direction of the port E pin drivers when pins are config-
ured for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit
configures the corresponding pin as an input. This register can be read or written at
any time.
Bits in this register determine the function of port E pins. Setting a bit assigns the cor-
responding pin to a bus control signal; clearing a bit assigns the pin to I/O port E.
RESET:
RESET:
NOT USED
NOT USED
NOT USED
Freescale Semiconductor, Inc.
For More Information On This Product,
8
Go to: www.freescale.com
REGISTER SUMMARY
PEPA7
DATA8
7
8
8
PEPA6
DATA8
6
DDE7
PE7
7
U
7
0
PEPA5
DATA8
5
DDE6
PE6
U
6
6
0
PEPA4
DATA8
DDE5
PE5
4
U
5
5
0
DDE4
PEPA3
DATA8
PE4
U
4
4
0
3
$YFFA11, $YFFA13
DDE3
PE3
U
3
3
0
PEPA2
DATA8
2
DDE2
PE2
U
2
2
0
PEPA1
DATA8
1
DDE1
$YFFA08
$YFFA15
$YFFA17
PE1
U
1
1
0
PEPA0
DATA8
DDE0
D-17
PE0
0
0
U
0
0
D