MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 153

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

6.4.3.4 Parity Checking
6.4.3.5 Transmitter Operation
MC68331
USER’S MANUAL
where SCBR is in the range {1, 2, 3,..., 8191}.
The SCI receiver operates asynchronously. An internal clock is necessary to synchro-
nize with an incoming data stream. The SCI baud clock generator produces a receive
time (RT) sampling clock with a frequency 16 times that of the SCI baud clock. The
SCI determines the position of bit boundaries from transitions within the received
waveform, and adjusts sampling points to the proper positions within the bit period.
The parity type (PT) bit in SCCR1 selects either even (PT = 0) or odd (PT = 1) parity.
PT affects received and transmitted data. The parity enable (PE) bit in SCCR1 deter-
mines whether parity checking is enabled (PE = 1) or disabled (PE = 0). When PE is
set, the MSB of the data in a frame is used for the parity function. For transmitted data,
a parity bit is generated; for received data, the parity bit is checked. When parity check-
ing is enabled, the parity flag (PF) in the SCI status register (SCSR) is set if a parity
error is detected.
Enabling parity affects the number of data bits in a frame, which can in turn affect
frame size. Table 6-6 shows possible data and parity formats.
The transmitter consists of a serial shifter and a parallel data register (TDR) located in
the SCI data register (SCDR). The serial shifter cannot be directly accessed by the
CPU. The transmitter is double-buffered, which means that data can be loaded into
the TDR while other data is shifted out. The transmitter enable (TE) bit in SCCR1 en-
ables (TE = 1) and disables (TE = 0) the transmitter.
Shifter output is connected to the TXD pin while the transmitter is operating (TE = 1,
or TE = 0 and transmission in progress). Wired-OR operation should be specified
when more than one transmitter is used on the same SCI bus. The wired-OR mode
select bit (WOMS) in SCCR1 determines whether TXD is an open-drain (wired-OR)
output or a normal CMOS output. An external pull-up resistor on the TXD pin is nec-
essary for wired-OR operation. WOMS controls TXD function whether the pin is used
for SCI transmissions (TE = 1) or as a general-purpose I/O pin.
Data to be transmitted is written to TDR, then transferred to the serial shifter. The
transmit data register empty (TDRE) flag in SCSR shows the status of TDR. When
TDRE = 0, TDR contains data that has not been transferred to the shifter. Writing to
SCI Baud Clock Rate
Table 6-6 Effect of Parity Checking on Data Size
Freescale Semiconductor, Inc.
For More Information On This Product,
=
M
0
0
1
1
System Clock
----------------------------------- -
32 SCBR
QUEUED SERIAL MODULE
PE
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0
1
0
1
8 Data Bits
7 Data Bits, 1 Parity Bit
9 Data Bits
8 Data Bits, 1 Parity Bit
Result
6-27
6