MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 64

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4
1. The CPU32 does not support misaligned transfers.
2. Three-byte transfer cases occur only as a result of a long word to byte transfer.
4.4.5 Operand Transfer Cases
4.5 Bus Operation
4-22
Num
10
11
12
13
1
2
3
4
5
6
7
8
9
The largest amount of data that can be transferred by a single bus cycle is an aligned
word. If the MCU transfers a long-word operand through a 16-bit port, the most signif-
icant operand word is transferred on the first bus cycle and the least significant oper-
and word is transferred on a following bus cycle.
Table 4-13 is a summary of how operands are aligned for various types of transfers.
OPn entries are portions of a requested operand that are read or written during a bus
cycle and are defined by SIZ1, SIZ0, and ADDR0 for that bus cycle. The following
paragraphs discuss all the allowable transfer cases in detail.
Internal microcontroller modules are typically accessed in two system clock cycles,
with no wait states. Regular external bus cycles use handshaking between the MCU
and external peripherals to manage transfer size and data. These accesses take three
system clock cycles, again with no wait states. During regular cycles, wait states can
be inserted as needed by bus control logic. Refer to 4.5.2 Regular Bus Cycles for
more information.
Fast-termination cycles, which are two-cycle external accesses with no wait states,
use chip-select logic to generate handshaking signals internally. Chip-select logic can
also be used to insert wait states before internal generation of handshaking signals.
Refer to 4.5.3 Fast Termination Cycles and 4.8 Chip Selects for more information.
Bus control signal timing, as well as chip-select signal timing, are specified in APPEN-
DIX A ELECTRICAL CHARACTERISTICS. Refer to the SIM Reference Manual (SIM-
RM/AD) for more information about each type of bus cycle.
The MCU is responsible for de-skewing signals it issues at both the start and the end
of a cycle. In addition, the MCU is responsible for de-skewing acknowledge and data
signals from peripheral devices.
Byte to 8-Bit Port (Even/Odd)
Byte to 16-Bit Port (Even)
Byte to 16-Bit Port (Odd)
Word to 8-Bit Port (Aligned)
Word to 8-Bit Port (Misaligned)
Word to 16-Bit Port (Aligned)
Word to 16-Bit Port (Misaligned)
Long Word to 8-Bit Port (Aligned)
Long Word to 8-Bit Port (Misaligned)
Long Word to 16-Bit Port (Aligned)
Long Word to 16-Bit Port (Misaligned)
3 Byte to 8-Bit Port (Aligned)
3 Byte to 8-Bit Port (Misaligned)
Transfer Case
Freescale Semiconductor, Inc.
Table 4-13 Operand Transfer Cases
For More Information On This Product,
2
1
SYSTEM INTEGRATION MODULE
2
1
Go to: www.freescale.com
1
1
[1:0]
SIZ
01
01
01
10
10
10
10
00
10
00
10
11
11
ADDR0 DSACK
X
0
1
0
1
0
1
0
1
0
1
0
1
[1:0]
10
01
01
10
10
11
01
10
10
01
01
10
10
DATA
[15:8]
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
Read Cycles
—
—
—
DATA
[7:0]
OP0
OP1
OP0
OP1
OP0
—
—
—
—
—
—
—
—
DATA
[15:8]
(OP0)
(OP0)
(OP0)
Write Cycles
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
USER’S MANUAL
DATA
(OP0)
(OP0)
(OP1)
(OP0)
(OP1)
(OP0)
(OP1)
(OP0)
[7:0]
OP0
OP1
OP0
OP1
OP0
MC68331
Cycle
Next
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13
12
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1
1
2
6
2
5
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