MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 62

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4
4.4.1.10 Halt Signal
4.4.1.11 Autovector Signal
4.4.2 Dynamic Bus Sizing
4-20
The internal bus monitor can generate the BERR signal for internal and internal-to-ex-
ternal transfers. An external bus master must provide its own BERR generation and
drive the BERR pin, because the internal BERR monitor has no information about
transfers initiated by an external bus master. Refer to 4.5.6 External Bus Arbitration
for more information.
The halt signal (HALT) can be asserted by an external device for debugging purposes
to cause single bus cycle operation or (in combination with BERR) a retry of a bus cy-
cle in error. The HALT signal affects external bus cycles only, so a program not requir-
ing the use of external bus may continue executing, unaffected by the HALT signal.
When the MCU completes a bus cycle with the HALT signal asserted, DATA[15:0] is
placed in the high-impedance state, and bus control signals are driven inactive; the ad-
dress, function code, size, and read/write signals remain in the same state. If HALT is
still asserted once bus mastership is returned to the MCU, the address, function code,
size, and read/write signals are again driven to their previous states. The MCU does
not service interrupt requests while it is halted. Refer to 4.5.5 Bus Exception Control
Cycles for further information.
The autovector signal AVEC can be used to terminate external interrupt acknowledge
cycles. Assertion of AVEC causes the CPU32 to generate vector numbers to locate an
interrupt handler routine. If it is continuously asserted, autovectors are generated for
all external interrupt requests. AVEC is ignored during all other bus cycles. Refer to
4.7 Interrupts for more information. AVEC for external interrupt requests can also be
supplied internally by chip-select logic. Refer to 4.8 Chip Selects for more information.
The autovector function is disabled when there is an external bus master. Refer to
4.5.6 External Bus Arbitration for more information.
The MCU dynamically interprets the port size of an addressed device during each bus
cycle, allowing operand transfers to or from 8-bit and 16-bit ports.
During an operand transfer cycle, an external device signals its port size and indicates
completion of the bus cycle to the MCU through the use of the DSACK inputs, as
shown in Table 4-12. Chip-select logic can generate data and size acknowledge sig-
nals for an external device. Refer to 4.8 Chip Selects for further information.
If the CPU is executing an instruction that reads a long-word operand from a 16-bit
port, the MCU latches the 16 bits of valid data and then runs another bus cycle to ob-
DSACK1
1
1
0
0
Freescale Semiconductor, Inc.
Table 4-12 Effect of DSACK Signals
For More Information On This Product,
DSACK0
SYSTEM INTEGRATION MODULE
1
0
1
0
Go to: www.freescale.com
Insert Wait States in Current Bus Cycle
Complete Cycle — Data Bus Port Size is 8 Bits
Complete Cycle — Data Bus Port Size is 16 Bits
Reserved
Result
USER’S MANUAL
MC68331