MC68331CEH20 Freescale Semiconductor, MC68331CEH20 Datasheet - Page 156

• Manufacturer Part Number: MC68331CEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

6
6.4.3.8 Receiver Wakeup
6-30
The SCI receiver has both short and long idle-line detection capability. Idle-line detec-
tion is always enabled. The idle line type (ILT) bit in SCCR1 determines which type of
detection is used. When an idle line condition is detected, the IDLE flag in SCSR is set.
For short idle-line detection, the receiver bit processor counts contiguous logic one bit-
times whenever they occur. Short detection provides the earliest possible recognition
of an idle line condition, because the stop bit and contiguous logic ones before and
after it are counted. For long idle-line detection, the receiver counts logic ones after
the stop bit is received. Only a complete idle frame causes the IDLE flag to be set.
In some applications, CPU overhead can cause a bit-time of logic level one to occur
between frames. This bit-time does not affect content, but if it occurs after a frame of
ones when short detection is enabled, the receiver flags an idle line.
When the idle line interrupt enable (ILIE) bit in SCCR1 is set, an interrupt request is
generated when the IDLE flag is set. The flag is cleared by reading SCSR and SCDR
in sequence. IDLE is not set again until after at least one frame has been received
(RDRF = 1). This prevents an extended idle interval from causing more than one in-
terrupt.
The receiver wakeup function allows a transmitting device to direct a transmission to
a single receiver or to a group of receivers by sending an address frame at the start of
a message. Hardware activates each receiver in a system under certain conditions.
Resident software must process address information and enable or disable receiver
operation.
A receiver is placed in wakeup mode by setting the receiver wakeup (RWU) bit in
SCCR1. While RWU is set, receiver status flags and interrupts are disabled. Although
the CPU can clear RWU, it is normally cleared by hardware during wakeup.
The WAKE bit in SCCR1 determines which type of wakeup is used. When WAKE = 0,
idle-line wakeup is selected. When WAKE = 1, address-mark wakeup is selected. Both
types require a software-based device addressing and recognition scheme.
Idle-line wakeup allows a receiver to sleep until an idle line is detected. When an idle-
line is detected, the receiver clears RWU and wakes up. The receiver waits for the first
frame of the next transmission. The byte is received normally, transferred to register
RDR, and the RDRF flag is set. If software does not recognize the address, it can set
RWU and put the receiver back to sleep. For idle-line wakeup to work, there must be
a minimum of one frame of idle line between transmissions. There must be no idle time
between frames within a transmission.
Address-mark wakeup uses a special frame format to wake up the receiver. When the
MSB of an address-mark frame is set, that frame contains address information. The
first frame of each transmission must be an address frame. When the MSB of a frame
is set, the receiver clears RWU and wakes up. The byte is received normally, trans-
ferred to register RDR, and the RDRF flag is set. If software does not recognize the
address, it can set RWU and put the receiver back to sleep. Address-mark wakeup al-
Freescale Semiconductor, Inc.
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USER’S MANUAL
MC68331