MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 99

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9.3.2 SIOP Status Register
The SIOP status register (SSR) is located at address $000B and contains two read-only bits.
shows the position of each bit in the register and indicates the value of each bit after reset.
SPIF — Serial Port Interrupt Flag
DCOL — Data Collision Bit
Freescale Semiconductor
The SPIF is a read-only status bit that is set on the last rising edge of SCK and indicates that a data
transfer has been completed. It has no effect on any future data transfers and can be ignored. The
SPIF bit can be cleared by reading the SSR followed by a read or write of the SDR or by writing a logic
1 to the SPIR bit in the SCR. If the SPIF is cleared before the last rising edge of SCK it will be set again
on the last rising edge of SCK. Reset clears the SPIF bit.
The DCOL is a read-only status bit which indicates that an illegal access of the SDR has occurred. The
DCOL bit will be set when reading or writing the SDR after the first falling edge of SCK and before SPIF
is set. Reading or writing the SDR during this time will result in invalid data being transmitted or
received. The DCOL bit is cleared by reading the SSR (when the SPIF bit is set) followed by a read or
write of the SDR. If the last part of the clearing sequence is
done after another transfer has started, the DCOL bit will be set again. Reset clears the DCOL bit.
1 = Serial transfer complete, serial interrupt if the SPIE bit in SCR is set
0 = Serial transfer in progress or serial interface idle
1 = Illegal access of the SDR occurred
0 = No illegal access of the SDR detected
Address:
Reset:
Read:
Write:
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
$000B
SPIF
Bit 7
SPR1
0
0
0
1
1
Figure 9-5. SIOP Status Register (SSR)
= Unimplemented
DCOL
Table 9-1. SIOP Clock Rate Selection
6
0
SPR0
0
1
0
1
5
0
0
4
0
0
Oscillator Frequency
SIOP Clock Rate
3
0
0
Divided by:
64
32
16
8
2
0
0
1
0
0
Bit 0
0
0
SIOP Registers
Figure 9-5
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