MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 43

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 5
Resets
5.1 Introduction
This section describes the five reset sources and how they initialize the microcontroller unit (MCU). A
reset immediately stops the operation of the instruction being executed, initializes certain control bits, and
loads the program counter with a user-defined reset vector address. These conditions produce a reset:
Figure 5-1
Freescale Semiconductor
•
•
•
•
•
Initial power-up of device (power-on reset)
A logic 0 applied to the RESET pin (external reset)
Timeout of the computer operating properly (COP) watchdog (COP reset)
Low voltage applied to the device (LVR reset)
Fetch of an opcode from an address not in the memory map (illegal address reset)
RESET
V
DD
shows a block diagram of the reset sources and their interaction.
MASK OPTION REGISTER ($1FF1)
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
ILLEGAL ADDRESS RESET
LOW-VOLTAGE RESET
POWER-ON RESET
COP WATCHDOG
CLOCKED
3-CYCLE
1-SHOT
Figure 5-1. Reset Sources
INTERNAL
ADDRESS BUS
INTERNAL DATA BUS
D
RESET
LATCH
S
R
RST
TO CPU
AND
SUBSYSTEMS
INTERNAL
CLOCK
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