MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 103

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.3 Core Timer Counter Register
A 15-stage ripple counter driven by a divide-by-eight prescaler is the basis of the core timer. The value of
the first eight stages is readable at any time from the read-only timer counter register as shown in
Figure
Power-on clears the entire counter chain and begins clocking the counter. After the startup delay (16 or
4064 internal bus cycles depending on the DELAY bit in the mask option register (MOR)), the power-on
reset circuit is released, clearing the counter again and allowing the MCU to come out of reset.
Each count of the timer counter register takes eight oscillator cycles or four cycles of the internal bus. A
timer overflow function at the eighth counter stage allows a timer interrupt every 2048 oscillator clock
cycles or every 1024 internal bus cycles.
10.4 COP Watchdog
Four counter stages at the end of the core timer make up the computer operating properly (COP)
watchdog which can be enabled by the COPEN bit in the MOR. The COP watchdog is a software error
detection system that automatically times out and resets the MCU if the COP watchdog is not cleared
Freescale Semiconductor
MHz
TOF = 1/(f
488
4.2
counting rate of the COP watchdog. Reset sets RT1 and RT0, selecting the longest COP timeout
period and longest real-time interrupt period.
Interrupt Period
(Microseconds)
Timer Overflow
@ f
10-3.
OSC
1024
MHz
2.0
OSC
(MHz)
Address:
÷ 2
Changing RT1 and RT0 when a COP timeout is imminent or uncertain may
cause a real-time interrupt request to be missed or an additional real-time
interrupt request to be generated. Clear the COP timer just before changing
RT1 and RT0.
2048
Reset:
MHz
Read:
Write:
1.0
Table 10-1. Core Timer Interrupt Rates and COP Timeout Selection
11
)
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
RT1
0
0
1
1
$0009
Bit 7
Bit 7
0
Figure 10-3. Core Timer Counter Register (CTCR)
RT0
0
1
0
1
= Unimplemented
divided
= f
6
6
0
Rate
RTI
by:
2
2
2
2
OSC
15
16
17
18
MHz
7.80
15.6
31.2
62.4
5
5
0
4.2
Interrupt Period
(Milliseconds)
@ f
Real-Time
OSC
NOTE
(RTI)
MHz
16.4
32.8
65.5
131
2.0
4
4
0
(MHz)
MHz
32.8
65.5
131
262
1.0
3
3
0
54.6
Min
109
218
437
4.2 MHz
2
2
0
62.4
Max
125
250
499
COP = 7-to-8 RTI Periods
COP Timeout Period
(Milliseconds)
@ f
Min
115
229
459
918
Core Timer Counter Register
1
1
0
2.0 MHz
OSC
(MHz)
1049
Max
131
262
524
Bit 0
Bit 0
0
1835
Min
229
459
918
1.0 MHz
1049
2097
Max
262
524
103