MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 52

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Operating Modes
6.3.1 Stop Mode
The STOP instruction puts the MCU in a mode with the lowest power consumption and affects the MCU
as follows:
The STOP instruction does not affect any other bits, registers, or I/O lines.
The following conditions bring the MCU out of stop mode:
When the MCU exits stop mode, processing resumes after a stabilization delay of 16 or 4064 internal bus
cycles, depending on the state of the DELAY bit in the MOR.
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Turns off the central processor unit (CPU) clock and all internal clocks by stopping both the external
pin oscillator and the internal low-power oscillator. The selection of the oscillator by the OM1 and
OM2 bits in the ISCR is not affected. The stopped clocks turn off the COP watchdog, the core timer,
the programmable timer, the analog subsystem, and the SIOP.
Removes any pending core timer interrupts by clearing the core timer interrupt flags (CTOF and
RTIF) in the core timer status and control register (CTSCR)
Disables any further core timer interrupts by clearing the core timer interrupt enable bits (CTOFE
and RTIE) in the CTSCR
Removes any pending programmable timer interrupts by clearing the timer interrupt flags (ICF,
OCF, and TOF) in the timer status register (TSR)
Disables any further programmable timer interrupts by clearing the timer interrupt enable bits (ICIE,
OCIE, and TOIE) in the timer control register (TCR)
Enables external interrupts via the IRQ/V
register (ISCR). External interrupts are also enabled via the PA0 through PA3 pins, if the port A
interrupts are enabled by the PIRQ bit in the mask option register (MOR).
Enables interrupts in general by clearing the I bit in the condition code register
An external interrupt signal on the IRQ/V
the program counter with the contents of locations $1FFA and $1FFB.
An external interrupt signal on a port A external interrupt pin — If selected by the PIRQ bit in the
MOR, a low-to-high transition on a PA3–PA0 pin loads the program counter with the contents of
locations $1FFA and $1FFB.
External reset — A logic 0 on the RESET pin resets the MCU and loads the program counter with
the contents of locations $1FFE and $1FFF.
Execution of the STOP instruction without setting the SWAIT bit in the MOR
will cause the oscillators to stop, and, therefore, disable the COP watchdog
timer. If the COP watchdog timer is to be used, stop mode should be
changed to halt mode as described in
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
PP
PP
NOTE
pin — A high-to-low transition on the IRQ/V
pin by setting the IRQE bit in the IRQ status and control
6.3.3 Halt
Mode.
Freescale Semiconductor
PP
pin loads