MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 33

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 4
Interrupts
4.1 Introduction
An interrupt temporarily stops normal program execution to process a particular event. An interrupt does
not stop the execution of the instruction in progress, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the central processor unit (CPU)
registers on the stack and loads the program counter with a user-defined vector address.
4.2 Interrupt Vectors
Table 4-1
Freescale Semiconductor
Reset
Software
interrupt (SWI)
External
interrupt (IRQ)
Core timer
interrupts
Programmable
timer interrupts
Serial interrupt
Analog interrupt
1. COPEN enables the COP watchdog timer.
2. PIRQ enables port A external interrupts on PA0–PA3.
Function
summarizes the reset and interrupt sources and vector assignments.
If more than one interrupt request is pending, the CPU fetches the vector of
the higher priority interrupt first. A higher priority interrupt does not actually
interrupt a lower priority interrupt service routine unless the lower priority
interrupt service routine clears the I bit.
Power-on logic
RESET pin
Low-voltage reset
Illegal address reset
COP watchdog
User code
IRQ/V
PA3 pin
PA2 pin
PA1 pin
PA0 pin
TOF bit
RTIF bit
ICF bit
OCF bit
TOF bit
SPIF bit
CPF1 bit
CPF2 bit
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
PP
Source
pin
Table 4-1. Reset/Interrupt Vector Addresses
COPEN
Control
PIRQ
MOR
Bit
—
—
—
—
—
—
—
(2)
(1)
NOTE
Hardware
Global
Mask
I bit
I bit
I bit
I bit
I bit
—
—
Software
TOFE bit
IRQE bit
OCIE bit
TOIE bit
SPIE bit
CPIE bit
RTIE bit
ICIE bit
Local
Mask
—
—
(1 = Highest)
Same priority
as instruction
Priority
1
2
3
4
5
6
$1FFC–$1FFD
$1FFE–$1FFF
$1FFA–$1FFB
$1FF8–$1FF9
$1FF6–$1FF7
$1FF4–$1FF5
$1FF2–$1FF3
Address
Vector
33